A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability

We propose a method of partitioning the set of all ip-ops in a circuit for multiple clock testing. In the multiple clock testing, ip-ops are partitioned into diierent groups and each group of ip-ops has an independent clock control. In our method, we use a test generator assuming an independent clock control for each ip-op. We than determine correlation between clock activity for all pairs of ip-ops. This information is than used to an optimal or near optimal partition of ip-ops in. Through experiments, we demonstrate that our partitioning method increases fault coverage and reduces test length with almost no hardware overhead or performance penalty.